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keypad decoder and i/o port expander data sheet adp5586 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features 16-element fifo for event recording 10 configurable i/os allowing for such functions as keypad decoding for a matrix of up to 5 5 key press/release interrupts gpio functions gpi with selectable interrupt level 100 k or 300 k pull-up resistors 300 k pull-down resistors gpo with push-pull or open drain programmable logic block pulse generators periods and on times above 30 sec in 125 ms increments up to 255 ms in 1 ms increments reset generator i 2 c interface with fast-mode plus (fm+) support of up to 1 mhz open-drain interrupt output 16-ball wlcsp, 1.59 mm 1.59 mm applications keypad entries and input/output expansion capabilities smartphones, remote controls, and cameras healthcare, industrial, and instrumentation functional block diagram sda gpi scan and decode uvlo por i 2 c interface oscillator registers key scan and decode logic i/o config int rst/r5 scl v dd adp5586 gnd pulse gen 1 pulse gen 2 reset gen r0 r3 r1 r2 r4 c0 c1 c2 c3 c4 11148-001 figure 1. general description the adp5586 is a 10-input/output port expander with a built-in keypad matrix decoder, programmable logic, reset generator, and pulse generators. input/output expander ics are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). i/o expanders can be used to increase the number of i/os available to a processor or to reduce the number of i/os required through interface connectors for front panel designs. the adp5586 handles all key scanning and decoding and can flag the main processor, via an interrupt line, that new key events have occurred. gpi changes and logic changes can also be tracked as events via the fifo, eliminating the need to monitor different registers for event changes. the adp5586 is equipped with a fifo to store up to 16 events. events can be read back by the processor via an i 2 c-compatible interface. the adp5586 eliminates the need for the main processor to monitor the keypad, thus reducing power consumption and/or increasing processor bandwidth for performing other functions. the programmable logic functions allow common logic require- ments to be integrated as part of the gpio expander, thus saving board area and cost.
adp5586 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 theory of operation ........................................................................ 7 device enable ................................................................................ 8 device overview .......................................................................... 8 functional description .................................................................... 9 event fifo .....................................................................................9 key scan control ........................................................................ 10 gpi input ..................................................................................... 13 gpo output ................................................................................ 13 logic block .................................................................................. 14 reset block .................................................................................. 15 interrupts ..................................................................................... 15 pulse generators ......................................................................... 16 register interface ............................................................................ 17 register map ................................................................................... 19 detailed register descriptions ................................................. 21 applications schematic .................................................................. 41 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 revision history 3 /1 3 revision 0: initial version
data sheet adp5586 rev. 0 | page 3 of 44 specifications vdd = 1.8 v to 3.3 v, t a = t j = ? 40 c to + 85 c , unless otherwise noted . 1 table 1. parameter symbol test conditions/comments min typ max unit supply voltage vdd input voltage range vdd 1.65 3.6 v undervoltage lockout threshold uvlo vdd uvlo active, vdd fa lling 1.2 1.3 v uvlo inactive, vdd rising 1.4 1.6 v supply current standby current i stnby vdd = 1.65 v 1 4 a vdd = 3.3 v 1 10 a operating current ( one key press) i scan 1 s can = 10 ms, core_freq = 50 khz, scan active, 300 k? pull - up, vdd = 1.65 v 30 40 a i scan 2 s can = 10 ms, core_freq = 50 khz, scan active, 300 k? pull - up, vdd = 3.3 v 75 85 a pull - up, pull - down resistance pull -up option 1 50 100 150 k? option 2 150 300 450 k? pull - down 150 300 450 k? input lo gic level ( rst , scl, sda, r0, r1, r2, r3, r4, r5, c0, c1, c2, c3, c4) input voltage logic low v il 0.3 vdd v logic high v ih 0.7 vdd v input leakage current (per pin) v i-l eak 0.1 1 a push- pull output logi c level (r0, r1, r2, r3, r4, r5, c0, c1, c2, c3, c4 output voltage logic low v ol1 sink current = 10 ma , maximum of five gpios active simultaneously 0.4 v v ol2 sink current = 10 ma , all gpios active simultaneously 0.5 v logic high v oh source current = 5 ma 0.7 vdd v logic high output leakage current (per pin) v oh -l eak 0.1 1 a open - drain output logic level ( int , sda) output voltage logic low int v ol3 i sink = 10 ma 0.4 v sda v ol4 i sink = 20 ma 0.4 v logic high output leakage current (per pin) v oh -l eak 0.1 1 a logic propagation delay 125 300 ns f lip -f lop (ff) hold time 2 0 ns ff setup time 2 175 ns gpio debounce 2 70 s internal oscillator frequency 3 osc freq 720 800 880 khz 1 all limits at temperature extremes are guaranteed via correlation, using standard statistical quality control (sqc). typical values are at t a = 25c, vdd = 1.8 v. 2 guaranteed by design. 3 all timers are referenced from the base oscillator and have the same 10% accuracy.
adp5586 data sheet rev. 0 | page 4 of 44 i 2 c timing specifications table 2. parameter description min max unit i 2 c timing specifications delay from uvlo/rst inactive to i 2 c access 60 s f scl scl clock frequency 0 1000 khz t high scl high time 0.26 s t low scl low time 0.5 s t su; dat data setup time 50 ns t hd; dat data hold time 0 s t su; sta setup time for repeated start 0.26 s t hd; sta hold time for start/repeated start 0.26 s t buf bus free time for stop and start conditions 0.5 s t su; sto setup time for stop condition 0.26 s t vd; dat data valid time 0.45 s t vd; ack data valid acknowledge 0.45 s t r rise time for scl and sda 120 ns t f fall time for scl and sda 120 ns t sp pulse width of suppressed spike 0 50 ns c b 1 capacitive load for each bus line 550 pf 1 c b is the total capacitance of one bus line in picofarads (pf). timing diagram sda scl sda scl s sr ps first clock cycle ninth clock ninth clock 1/ f scl 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% t f t f t r t r t high t vd; dat t su; dat t su; sta t hd; dat t hd; sta t vd; ack t sp t su; sto t buf t low t hd; sta v il = 0.3v vdd v ih = 0.7v vdd 11148-002 figure 2. i 2 c interface timing diagram
data sheet adp5586 rev. 0 | page 5 of 44 absolute maximum ratings table 3 . parameter rating vdd to gnd ? 0.3 v to +4 v scl, sda, rst , int , r0, r1, r2, r3, r4, c0, c1, c2, c3, c4 ? 0.3 v to (vdd + 0.3 v) temperature range operating (ambien t) ? 40 c to +85 c 1 operating ( junction ) ? 40 c to +125 c storage ? 65 c to +150 c 1 in applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may need to be derated. maximum ambient temperatur e (t a (max) ) is dependent on the maximum operating junction temperature (t j (maxop) = 125 c), the maximum power dissipation of the device (p d (max) ), and the junction - to - ambient thermal resistance of the device /package in the application ( ja ), using the f ollowing equation: t a (max) = t j (maxop) ? ( ja p d (max) ). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condit ions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in com - bin ation. unless otherwise specified, all other voltages are referenced to gnd. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a printed circuit board (pcb) for surface - mount packages. table 4 . thermal resistance ja unit 16- ball wlcsp 62 c/w maximum power dissipation 70 mw e sd caution
adp5586 data sheet rev. 0 | page 6 of 44 pin configuration and fu nction descriptions int rst/r5 1 a b c d 234 c1 r2 vdd c2 sda r4 c3 r1 scl c4 r0 gnd c0 r3 ball a1 corner top view (ball side down) not to scale 11148-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description a1 vdd supply voltage input. a2 sda i 2 c data input/output. a3 scl i 2 c clock input. a4 gnd ground. b1 r0 gpio 1 (gpio alternate function: logic block output ly). this pin functions as row 0 when configured in keypad mode. b2 int open-drain interrupt output. b3 rst /r5 input reset signal (rst ). the reset signal function applies to all models except the adp5586acbz-01-r7. gpio 6/row 5 (r5). this function applie s only to the adp5586acbz-01-r7 model. b4 c0 gpio 7 (gpio alternate function: pulse_gen_1). this pi n functions as column 0 when configured in keypad mode. c1 r2 gpio 3 (gpio alternate function: logic block input lb). this pin functions as row 2 when configured in keypad mode. c2 r1 gpio 2 (gpio alternate function: logic block input la). this pin functions as row 1 when configured in keypad mode. c3 c1 gpio 8 (gpio alternate function: pulse_gen_2). this pi n functions as column 1 when configured in keypad mode. c4 c2 gpio 9. this pin functions as column 2 when configured in keypad mode. d1 r4 gpio 5 (gpio alternate function: reset_out). this pin functions as row 4 when configured in keypad mode. d2 r3 gpio 4 (gpio alternate function: logic block input lc). this pin functions as row 3 when configured in keypad mode. d3 c3 gpio 10. this pin functions as column 3 when configured in keypad mode. d4 c4 gpio 11. this pin functions as column 4 when configured in keypad mode.
data sheet adp5586 rev. 0 | page 7 of 44 theory of operation 11148-004 row 0 sda i 2 c interface i 2 c busy? oscillator registers i/o configuration int rst/r5* row 1 row 2 row 3 row 4 row 5 col 1 col 0 col 2 col 3 col 4 (r0) (r1) (r2) (r3) (r4) (rst/r5)* (c0) (c1) (c2) (c3) (c4) (r0) (r1) (r2) (r3) (r4) (c0) (c1) (c2) (c3) (c4) gpio 1 gpio 2 gpio 3 gpio 4 gpio 5 gpio 7 gpio 8 gpio 9 gpio 10 gpio 11 key event gpi event logic event scl v dd adp5586 gnd r0 r3 r1 r2 r4 c0 c1 c2 c3 c4 pulse control (c1) (c0) pulse_gen_1 pulse_gen_2 (rst/r5)* gpio 6 logic (r1) (r2) (r3) (r0) la lb lc ly (r4) reset_out rst reset gen gpi scan and decode key scan and decode fifo update uvlo por *r5 available on adp5586acbz-01-r7 only. figure 4. internal block diagram
adp5586 data sheet rev. 0 | page 8 of 44 device enable when sufficient voltage is applied to vdd and the rst pin is driven with a logic high level, the adp5586 starts up in standby mode with all settings at default. the user can configure the device via the i 2 c interface. when the rst pin is low, the adp5586 enters a reset state and all settings return to default. the rst pin features a debounce filter. if the adp5586acbz-01-r7 device model is used, the rst pin acts as an additional row pin (r5). to reset the part without a reset pin, either bring vdd below the uvlo threshold, or set the sw_reset bit to 1 (register 0x3d, bit 2). device overview the adp5586 contains 10 multiconfigurable input/output pins. each pin can be programmed to enable the device to carry out its various functions, as follows: ? keypad matrix decoding (five-column by five-row matrix maximum) ? general-purpose i/o expansion (up to 10 inputs/outputs) ? reset generator ? logic function building blocks (up to three inputs and one output) ? two pulse generators all 10 input/output pins have an i/o structure as shown in figure 5. i/o vdd 100k ? debounce 300k ? 300k ? i/o drive 11148-005 figure 5. i/o structure each i/o can be pulled up with a 100 k or 300 k resistor or pulled down with a 300 k resistor. for logic output drive, each i/o has a 5 ma pmos source and a 10 ma nmos sink for a push- pull type output. for open-drain output situations, the 5 ma pmos source is not enabled. for logic input applications, each i/o can be sampled directly or, alternatively, sampled through a debounce filter. the i/o structure shown in figure 5 allows for all gpi and gpo functions, as well as pwm and clock divide functions. for key matrix scan and decode, the scanning circuit uses the 100 k or 300 k resistor for pulling up the keypad row pins and the 10 ma nmos sinks for grounding the keypad column pins (see the key scan control section for details about key decoding). configuration of the device is carried out by programming an array of internal registers via the i 2 c interface. feedback of device status and pending interrupts can be flagged to an external processor by using the int pin. the adp5586 is offered with three feature sets. table 6 lists the options that are available for each model of the adp5586 . contact your local analog devices, inc., field applications engineers for availability and/or alternate configurations. table 6. matrix options by device model 1 model description ADP5586ACBZ-00-R7 gpio pull-down on startup 5-row 5-column matrix adp5586acbz-01-r7 row 5 added to gpios 6-row 5-column matrix adp5586acbz-03-r7 alternate i 2 c address (0x30) 5-row 5-column matrix 1 contact analog devices for availabilit y of configurations not shown here.
data sheet adp5586 rev. 0 | page 9 of 44 functional description event fifo before going into detail on the various blocks of the adp5586 , it is important to understand the function of the event fifo that is featured in t he adp5586 . the event fifo ( register 0x03 to register 0x12) can record as many as 16 events. by default, the fifo primarily records key eve nts , such as key press and key release. however , it is possible to configure the general - purpose input (gpi) and logic activity t o generate event information on the fifo , as well. an event count, ec[4:0] (register 0x02, bits[4:0]) , is composed of five bits and works in tandem with the fifo so that the user knows how many events are stored in the fifo. the fifo consists of sixteen 8- bit elements. bits[6:0] of each element st ore the event identifier, and bit 7 stores the event state. the user can read the top element of the fifo from any of the fifo_1 through fifo_16 registers. the adp5586 has multiple copies of the fifo register to allow reading of the complete fifo with a single i 2 c burst read. event1[7:0] event2[7:0] event3[7:0] event4[7:0] event13[7:0] event14[7:0] event15[7:0] event16[7:0] event5[7:0] event6[7:0] event7[7:0] event8[7:0] event9[7:0] event10[7:0] event11[7:0] event12[7:0] 7 gpi events ec[4:0] ovrflow_int key events logic events 6 5 4 3 2 1 0 fifo update event8_identifier[6:0] event8_state 11 148-006 figure 6 . breakdown of eventx[7:0] bits key 3 pressed key 3 released gpi 7 active ec = 3 key 3 released gpi 7 active ec = 2 gpi 7 active ec = 1 ec = 0 third read second read first read 11 148-007 figure 7 . fifo operation the fifo registers always poi nt to the top of the fifo (that is, the location of event1[7:0]). if the user tries to read back from any location in a fifo, data is always obtained from the top of th at fifo . this ensures that events can be read back only in the order in which they occurred , th ereby ensuring the integrity of the fifo system. as stated previously , some of the on - board functions of t he adp5586 can be programmed to generate events on the fifo. a fifo update control block manages updates to th e fifo. if an i 2 c transaction is accessing any of the fifo address locations, updates are paused until the i 2 c transaction is complete . a fifo overflow event occurs when more than 16 events are generated prior to an external processor reading a fifo and clear ing it. if an overflow condition occurs, the overflow interrupt status bit is set (ovrflow_int, register 0x01, bit 2) . a n interrupt is generated if an overflow interrupt is enabled, signaling to the processor that more than 16 events have occurred.
adp5586 data sheet rev. 0 | page 10 of 44 k ey scan control general the 10 input/output pins can be configured to decode a keypad matrix up to a maximum s ize of 25 switches (5 5 matrix) using the pin_config_a, pin_config_b, and pin_config_c registers (registers 0x3a through 0x3c). smaller matrices can also be configured, making the unused row and column pins available for other i/o functions. the r0 through r4 i/o pins comprise the rows of the keypad matrix. the c0 through c4 i/o pins comprise the columns of the keyp ad matrix. pins that are used as rows are pulled up via the internal 300 k (or 100 k ) resistors. pins that are used as columns are driven low via the internal nmos current sink. 1 2 3 4 5 6 7 8 9 r0 r1 r2 c2 c0 c1 3 3 keypad matrix key scan control vdd 11 148-008 figure 8 . simplified key scan block figure 8 shows a simplified representation of the key scan block us ing three row pins and three column pins connected to a small 3 3, nine - switch keypad matrix. when the key scanner is idle, the row pins ar e pulled high and the column pins ar e driven low. the key scanner operates by checking the row pins to see if they are low. if s witch 6 in the matrix is pressed, r1 c onnect s to c2. the key scan circuit sense s that one of the row pins has been pulled low, and a key scan cycle begins . key scannin g involves driving all column pins high, then driv ing each column pin low , one at a time , and sensing whether a row pin is low. all row/column pairs are scanned ; therefore, if multiple keys are pressed, they ar e detected. to pre ve nt a glitch or narrow press time from being registered as a valid key press, the key scanner requires that the key be presse d for two scan cycles. the key scanner has a wait time between each scan cycle ; therefore, the key must be pressed and held for at least this wait time to register as being pressed. if the key is continuously pressed , the key scanner continue s to scan and wait for as long as the key is pressed . if s witch 6 is released, the connection between r1 and c2 breaks , and r1 is pulled high. the key scanner requires that the key be released for two scan cycles because t he release of a key is not necessari ly in sync with the key scanner. u p to two full wait/scan cycles may be required for a key to register as released. when the key registers as released, and no other keys are pressed, the key scanner returns to idle mode. for the remainder of this d ata sheet , the press/release status of a key is represented as simply a logic signal in the figures . a logic high level represent s the key status as pressed , and a logic low level represent s released . this eliminates the need to draw individual row/column signals when describing key events. key x key released key released key pressed 11 148-009 figure 9 . logic low: key released ; logic high: key pressed
data sheet adp5586 rev. 0 | page 11 of 44 11 148-010 logic event 54321 10 9876 1514131211 2019181716 2524232221 3029282726 i/o configuration key event gpi event i 2 c busy? r0 r3r1 r2 r4 r5* c0 c1 c2 c3 c4 pin_config_a[7:0] pin_config_b[7:0] fifo pin_config_c[7:0] event_int ovrflow_int ec[4:0] reset_trig_time[3:0] reset_event_a[7:0] reset_event_b[7:0] reset_event_c[7:0] 31 33 36 32 35 34 reset_initiate fifo update key scan control column sink on/off row sense *r5 available on adp5586acbz-01-r7 only. figure 10 . detailed key scan block f igure 10 shows a detailed representation of the key scan block and its associated control and status signals. when all row and column pins are used, a matrix of 25 unique keys can be scanned. use the pin_config_a[ 5 :0] and pin_confi g_b[ 4 :0] registers (regi ster 0x3a and register 0x3b, respectively) to configure the i/os for keypad decoding. the number label on each key switch represents the event identifier that is recorded if that switch is pressed. if all row/column pins ar e confi g ured, it is possible to o bserve all 25 key identifiers on the fifo . if a smaller 2 2 matrix is configured, for example, by using the c2 and c3 column pins and the r1 and r2 row pins, only four event identifiers (8, 9, 13, and 14) can possibly be observed on the fifo , as shown in figure 10 . by default, t he adp5586 records key presses and rele ases on the fifo. figure 11 illustrates what h appens when a single key is pressed and released. initially, the key scanner is idle. when key 3 is pressed, the scanner begins scanning through all configured row/column pairs. after the scan wait time, the scanner again scans through all configured row/c olumn pairs and detects that key 3 has remained pressed, which sets the event_int interrupt bit (register 0x01, bit 0) . the event counter , ec[4:0] (register 0x02 , bits[4:0] ) , is then incremented to 1; event1 _identifier [6 :0] of the fifo is updated with its event identifi er set to 3; and its e vent 1_s tate bit is set to 1, indicating a key press. key 3 key 3 press key 3 release key scan event_int ec[4:0] fifo 1 2 1 0 0 0 3 3 0 0 11 148-0 11 figure 11 . press and release event the key scanner continues the scan/wait cycles while the key remains pressed. if the scanner detects that the key has been released for two consecutive scan cycles, the event counter , ec[4:0] , is incremented to 2, and event2 _identifier [6:0] of the fifo is updated with its event identifier set to 3. the e vent2_state bit is set to 0, indicating a release. the k ey scanner returns to idle mode because no other keys are pressed.
adp5586 data sheet rev. 0 | page 12 of 44 the event _int interrupt (register 0x01, bit 0) can be triggered by both press and release key events. as shown in figure 12 , if key 3 is pressed, event_int is asserted, ec[4:0] is updated, and the fifo is updated. during the time that the key remains pressed, it is possible for the fifo to be read, the event counter decremented to 0, and event_int cleared. when the key is finally released, event_int is asserted, the event counter is incremented, and the fifo is updated with the release event information. key 3 key 3 press key 32 release key scan event_int event_int cleared ec[4:0] fifo fifo read 0 0 0 0 0 0 0 0 fifo 1 0 0 0 3 0 0 0 fifo 1 0 1 0 0 0 0 3 0 0 0 11 148-012 figure 12 . asserting the event_int i nterrupt keyp ad extensio n as shown in figure 10 , the keypad can be extended if each row is connected directly to ground by a switch. if the switch placed between r0 and ground is pressed, the entir e row is grounded. when the key scanner completes scanning, it normally detects key 1 to key 5 as bein g pres sed ; h owever, this unique condi tion is decoded by the adp5586 , and key event 31 is assigned to it. up to five more key event assignments are possible, allowing th e keypad size to extend up to 30 . however, i f one of the extended keys is pressed, none of the keys on that row is detectable. the a ctivation of a ground key causes all other keys sharing that r ow to be undetectable. precharge time during a scan sequence, a row scans through the co lumns sequentially. each row/column combination is tested at a rate that is define d by the key_poll_time bits (r egister 0x3 9, bits [1:0]) . within each of these scan time s, each column is scanned for a time defined by the precharge_time bit (register 0x3 9 , b it 3) . as shown in figure 13 , the resistance capacitance (rc) time constant , which is defined by the series resistance (from pull - up/pull - down, for example ) and parallel capacitance that is seen on the individual c olumns , affects the sampling of a key press event. r1 scan active key 8 (r1, c2) sampled precharge time key 9 (r1, c3) sampled v c2 v c3 11148-013 figure 13 . precharge time the adp5586 sample s the state of the row/c olumn pairs near the end of the precharge time. by extending this time, higher rc time constants can be accommodated. for applic a tions that use physical buttons, the rc time constant is usually not an issue, but if external relay switches or multiple external mux es are attached to columns, the rc consta nt may increase. using a s maller pull - up resistor on the r ows (register 0x3 c , bit 7) reduce s the rc time constant. ghosting ghosting is an occurrence where , given certain key press combinations on a keypad matrix, a false positive reading of an additional key is detected. gh osting is created when three or more keys are pressed simultaneously on multiple rows or columns (see figure 14 ). key combinations that form a right angle on the keypad matrix may cause ghosting. col0 row0 row1 row2 row3 press ghost press press col1 col2 11 148-014 figure 14 . ghosting example: column 0/ row 3 is a ghost key due to a short among r ow 0, column 0, column 2, and row 3 during key pre ss the solution to ghosting is to select a keypad matrix layout that takes into account three ke y combinations that are most likely to be pressed together. multiple keys that are pressed across one row or across one column do not cause ghosting. staggering keys so that they do not share a column also avoids ghosting. the most common practice is to pl ace keys in the same row or column that are likely to be pressed at the same time . some examples of keys that are likely to be pressed at the same time are as follows: ? the navigation keys in combination with the s elect key ? the navigation keys in combination with the space bar ? the reset combination keys, such as ctrl + alt + del
data sheet adp5586 rev. 0 | page 13 of 44 gpi input each of the 10 input/output lines can be configured as a ge neral - purpose l ogic input line using the gpio_inp_en_a and gpio_inp_en_b registers (register 0x29 and register 0x2a) . gpio lines can be configured to allow both input and output at the same time. figure 15 shows a detailed represe ntation of the gpi scan and detect block and its associated control and status signals. gpi_int gpio 1 gpio 2 gpio 3 gpio 4 gpio 5 gpio 6 gpio 7 gpio 8 gpio 9 (r0) (r1) (r2) (r3) (r4) rst/(r5) (c0) (c1) (c2) gpio 10 gpio 11 (c3) (c4) gpi event key event ovrflow_int logic event gpi_int_level_a[7:0] gpi_int_level_b[7:0] gpi_interrupt_en_a[7:0] gpio_out_en_b[7:0] gpio_inp_en_a[7:0] gpio_inp_en_b[7:0] gpio_out_en_a[7:0] pin_config_b[7:0] pin_config_a[7:0] gpi_status_a[5:0] gpi_status_b[4:0] gpi_int_stat_a[5:0] gpi_event_en_a[7:0] gpi_interrupt_en_b[7:0] gpi_event_en_b[7:0] event_int gpi_int_stat_b[4:0] reset_trig_time[3:0] reset_event_a[7:0] reset_event_b[7:0] reset_event_c[7:0] [fifo1:fifo16] ec[4:0] fifo update i 2 c busy gpi scan control 11148-015 figur e 15 . gpi scan and detect block the current input state of each gpi can be read back using the gpi_status_x registers (register 0x15 and register 0x16) . each gpi can be programmed to generate an interrupt via the gpi_interrupt_en_ x registers (register 0x1f and register 0x20 ) . the in terrupt status is stored in the gpi_int_ stat_x registers (register 0x13 and register 0x14) . gpi interrupts can be programmed to trigger on the positive or negative edge by configuring the gpi_int_level_x registers (register 0x1b and register 0x1c) . if any gpi interrupt is triggered, the master gpi_int interrupt bit (register 0x01, bit 1) is also triggered. figure 16 show s a single gpi and how it affects its corre s pond - ing status and the interrupt status bits. gpi 4 gpi_status_a[3] gpi_interrupt_en_a[3] gpi_int_stat_a[3] gpi_int gpi_int_level_a[3] cleared by read cleared by write ?1? 11 148-016 figure 16 . single gpi example gpis can be programmed to generate fifo events via the gpi_event_en_x registers (register 0x1d and register 0x1e) . gpis in this mode do not generate gp i_int interrupts . i nstead , they generate event_int interrupts (register 0x01, bit 0) . figure 17 shows several gpi lines and their effect s on the fifo and event count , ec[4:0] . gpi 2 gpi scan event_int ec[4:0] 1 6 gpi 2 active gpi 4 gpi 7 2 3 4 5 gpi 7 active gpi 4 active gpi 4 inactive gpi 7 inactive gpi 2 inactive fifo 1 1 1 0 0 0 38 38 43 43 40 40 11 148-017 figure 17 . multiple gpi example the gpi scanner is idle until it detects a level transition. it then scans the gpi inputs and updates accordingly. after updating, it returns immediately to idle; it does not scan/wait, like the key scanner. as a result, the gpi scanne r can detect both edges of narrow pulses after they pass the 70 s input debounce filter. gpo output each of the 10 input/output lines can be configured as a general - purpose output (gpo) line using the gpio _out_en_a and gpio_out_en_b registers (register 0x27 and register 0x28). gpio lines can be configured to allow b oth in put and output at the same time (s ee figure 5 for a detailed diagram of the i/o structure ). gpo configuration and usage are programmed in the gpo_data_out_x and gpo_out_mode_x registers (register 0x23 to regi ster 0x26). see the detailed register descriptions section for more information .
adp5586 data sheet rev. 0 | page 14 of 44 logic block several of the adp5586 input/output lines can be used as inputs and outputs for implementing some common logic functions. the r1, r2, and r3 input/output pins can be used as inputs, and the r0 input/output pin can be used as an output for the logic b lock. when the r1, r2, and r3 input lines are used, the gpio_ 4 _inp_en, gpio_3_inp_en, and gpio_ 2 _inp_en bits (r egister 0x29 , bits [3:1] ) must be enabled to accept inputs. when the r0 pin is used as an output for the logic block , the gpio_1_out_en bit (r egister 0x27 , b it 0 ) must be enabled. t he outputs from the logic block can be configured to generate interrupts. they can also be configured to generate events on the fifo . figure 19 shows a detail ed diagram of the internal make up of the logic block, illustrating the possible lo gic functions that can be implemented. gpi event key event logic event (r1) la lc lb la_inv d clr q set lb_inv lc_inv ff_set ff_clr r3_extend_cfg logic_sel[2:0] ly_inv (r2) (r3) logic block ly (r0) logic_int logic_int_level logic_event_en ovrflow_int event_int reset_trig_time[3:0] reset_event_a[7:0] reset_event_b[7:0] reset_event_c[7:0] fifo ec[4:0] logic event/int generator i 2 c busy fifo update 11 148-018 figure 18 . logic block overview la_inv mux 000 001 sel[2:0] out 010 011 100 101 110 111 sel out 0 1 gnd and or xor ff in_la in_lb in_lc la la la in_la sel out 0 1 and in_la in_lb in_lc r3_extend_cfg = 1 logic_sel[2:0] ly_inv sel out 0 1 ly ly ly lb_inv sel out 0 1 lb lb lb in_lb lc_inv sel out 0 1 lc lc lc in_lc ff_set ff_clr sel out 0 1 or in_la in_lb in_lc and and or or sel out 0 1 xor in_la in_lb in_lc in_la in_lb in_lc xor xor d clr q set 0 1 sel out ff 11 148-019 figure 19 . logic b l ock internal makeup
data sheet adp5586 rev. 0 | page 15 of 44 reset block the adp5586 features a reset block that can generate reset con- ditions if certain events are detected simultaneously. up to three reset trigger events can be programmed for reset_out. the event scan control blocks monitor whether these events are present for the duration of reset_trig_time[3:0] (register 0x2e, bits[5:2]). if they are present, reset-initiate signals are sent to the reset generator blocks. the generated reset signal pulse width is programmable. reset_pulse_width[1:0] reset_trig_time[3:0] reset_event_a[7:0] reset_event_b[7:0] reset_event_c[7:0] rst_passthru_en rst (r4) reset_out reset_ initiate reset gen key scan control gpi scan control logic block control 11148-020 figure 20. reset blocks the reset_out signal uses the r4 i/o pin as its output, which must be configured via the gpio_5_out_en bit (register 0x27, bit 4) to enable the output function. a pass- through mode also allows the rst pin function to be output on the r4 pin. the reset generation signals are useful in situations where the system processor has locked up and the system is unresponsive to input events. the user can press one of the reset event combi- nations and initiate a system-wide reset, which eliminates the need to remove the battery from the system and perform a hard reset. the use of the immediate trigger time setting (see table 55) is recommended only in very low noise conditions with good debounce; otherwise, false triggering may occur. interrupts the int pin can be asserted low if any of the internal interrupt sources is active. the user can select which internal interrupts interact with the external interrupt pin in register 0x3e (see table 71). register 0x3d allows the user to choose whether the external interrupt pin remains asserted, or deasserts for 50 s and then reasserts, as in the case where multiple internal interrupts are asserted and one is cleared (see table 70). event_int event_ien int drive int int_cfg gpi_int gpi_ien logic_int logic_ien ovrflow_int ovrflow_ien 11148-021 figure 21. asserting int low
adp5586 data sheet rev. 0 | page 16 of 44 pulse generators the adp5586 contains two pulse generat ors that are suitable for driving indicator led drive signals, as well as watchdog timers and other extended time pulsed applications. the adp5586 allows for eight bits of definition for both the on time and period of the generated pulse. t o allow fo r extended timings, the user can choose between a 1 ms clock and a 125 ms clock to increment these timers . the pulse_gen_1_period and pulse_gen_2_ period registers (register 0x30 and register 0x33 , resp ectively ) define the period s of the two pulse generators. c ho osing a clock period of 125 ms in the pulse_gen _config register (register 0x35, bit 1 and bit 5 ) allows for the setting of pulse generator period s of up to 31.875 sec . s etting the pulse_gen_x_on_ clk bit to a step size of 125 ms and the pulse_gen_ x _prd_clk bit to a step size of 1 ms is not a supported configuration. t o support active low applications, a signal inv ersion can be programmed in the pulse_gen_config register, using bit 7 and bit 3 (pul se_gen_x_inv) . delays can be introduced to create synchronized offsets between the channels. if both channe ls are enabled at the same time ( that is, enabled from the same i 2 c write) , the difference in delays is the offset between the channels. if a single channel is active and delays are to be synchronized , the user must first disable both pulse generators before enabling both pulse generators with the same i 2 c write command. the d elay counter uses the same clock selection as the p eriod counter . see table 56 through table 61 for more details. to enable pulse generator output on c1 and/or c0 , the gpio_8_out_en bit and/or the gpio_7_out_en bit (register 0x28, bits [1:0]) must be enabled. 11148-022 pulse_gen_x pulse_gen_x_on_time[7:0] 125ms clock 1ms clock pulse_gen_x_on_clk pulse_gen_x_prd_clk pulse_gen_x_period[7:0] pulse_gen_x_delay[7:0] pulse generator pulse_gen_x_inv 0 1 0 1 on time counter x period counter x delay counter x pulse_gen_x_en f igure 22 . pulse generator block diagram 11148-023 period 1 period 2 pulse_gen_1 on time 1 pulse_gen_2 on time 2 sda/scl delay 1 delay 2 figure 23 . example pulse generator timing
data sheet adp5586 rev. 0 | page 17 of 44 register interface register access to the adp5586 is acq uired via its i 2 c- compatible serial interface. the interface can support clock frequencies of up to 1 mhz. if the user is accessing the fifo or key event counter (kec), fifo/kec updates are paused. if the clock frequency is very low, events may not be reco rded in a timely manner. fifo or kec updates can happen up to 23 s after an interrupt is asserted because of the number of i 2 c cycles required to perform an i 2 c read or write. this delay should not present an issue to the user. figure 24 shows a typical write sequence for programming an internal register. the cycle begins with a start condition, followed by the hard coded 7- bit device address , which for the adp5586 is 0x34 , followed by the r/ w bit set to 0 for a write cycle. the adp5586 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5586 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5586 acknowledges the data byte by pulling the data line low. a stop condition completes the sequence. figure 25 shows a typical multibyte write sequence for program - ming in ternal registers. the cycle begins with a start condition followed by the 7 - bit device address (0x34), followed by the r/ w bit , which is s et to 0 for a write cycle. the adp5586 6 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5 586 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5586 acknowledges the data byte by pulling the data line low. the p ointe r address is then incremented to write the next data byte, until it finishes writing the n data byte. the adp5586 pulls the data line low after every byte, and a stop condition completes the sequ ence. figure 26 shows a typical byte read sequence for reading inter - nal registers. the cycle begins with a start condition followed by the 7 - bit device address, followed by the r/ w bit set to 0 for a write cycle. the adp5586 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5586 acknowledges the register pointer byte by pulling the data line low. a start condi - tion is repeated, followed by the 7 - bit device address ( 0x34 ), followed by the r/ w bit set to 1 for a re ad cycle. the adp5586 acknowledges the address byte by pulling the data line low. the 8- bit data is then read. the host pulls the data line high (no acknowledge), and a stop condition completes t he sequence. start 0 = write 7-bit device address adp5586 ack 8-bit register pointer 8-bit write data 0 0 0 0 adp5586 ack adp5586 ack stop 11 148-024 figure 24 . i 2 c single byte write sequence start 0 = write 7-bit device address adp5586 ack 8-bit register pointer write byte 1 write byte 2 write byte n 0 0 0 0 0 0 0 adp5586 ack adp5586 ack adp5586 ack adp5586 ack adp5586 ack stop 11 148-025 figure 25 . i 2 c multibyte write sequence start 0 = write 7-bit device address 7-bit device address adp5586 ack 8-bit register pointer 8-bit read data 0 0 0 1 0 1 repeat start 1 = read adp5586 ack adp5586 ack no ack stop 11 148-026 figure 26 . i 2 c single byte read sequence
adp5586 data sheet rev. 0 | page 18 of 44 figure 27 shows a typical multibyte read sequence for reading internal registers. the cycle begins with a start condition followed by the 7 - bit device address ( 0x34 ), followed by the r/ w bit set to 0 for a write cycle. th e adp5586 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5586 acknowl - edges th e register pointer byte by pulling the data line low. a start condition is repeated, followed by the 7 - bit device address ( 0x34 ), followed by the r/ w bit set to 1 for a read cycle. the adp5586 acknowledges the address byte by pulling the data line low. next, t he 8 - bit data is then read. the address pointer is then incremented to read the next data byte, and the host continues to pull the d ata line low for each byte (master acknowledge) until the n data byte is read . the host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence. start 0 = write 7-bit device address 7-bit device address adp5586 ack 8-bit register pointer read byte 1 read byte 2 read byte n 0 0 0 1 0 0 0 0 1 repeat start 1 = read adp5586 ack adp5586 ack master ack master ack master ack no ack stop 11 148-027 figure 27 . i 2 c multibyte read sequence
data sheet adp5586 rev. 0 | page 19 of 44 register map table 7 . reg add r reg ister name r/w 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 id r man_id rev_id 0x01 int_status r/w reserved logic_int reserved ovrflow_ int gpi_int event_int 0x02 statu s r reserved logic_stat reserved ec[4:0] 0x03 fifo_1 r event1_state event1_identifier[6:0] 0x04 fifo_2 r event2_state event2_identifier[6:0] 0x05 fifo_3 r event3_state event3_identifier[6:0] 0x06 fifo_4 r event4_state event4_identifier[6:0] 0x07 fifo_ 5 r event5_state event5_identifier[6:0] 0x08 fifo_6 r event6_state event6_identifier[6:0] 0x09 fifo_7 r event7_state event7_identifier[6:0] 0x0a fifo_8 r event8_state event8_identifier[6:0] 0x0b fifo_9 r event9_state event9_identifier[6:0] 0x0c fifo_1 0 r event10_state event10_identifier[6:0] 0x0d fifo_11 r event11_state event11_identifier[6:0] 0x0e fifo_12 r event12_state event12_identifier[6:0] 0x0f fifo_13 r event13_state event13_identifier[6:0] 0x10 fifo_14 r event14_state event14_identifier[6:0 ] 0x11 fifo_15 r event15_state event15_identifier[6:0] 0x12 fifo_16 r event16_state event16_identifier[6:0] 0x13 gpi_int_ stat_a r reserved gpi_6_int gpi_5_int gpi_4_int gpi_3_int gpi_2_int gpi_1_int 0x14 gpi_int_ stat_b r reserved gpi_11_int gpi_10_int gpi_9_int gpi_8_int gpi_7_int 0x15 gpi_status_a r reserved gpi_6_stat gpi_5_stat gpi_4_stat gpi_3_stat gpi_2_stat gpi_1_stat 0x16 gpi_status_b r reserved gpi_11_stat gpi_10_stat gpi_9_stat gpi_8_stat gpi_7_stat 0x17 r_pull_ config_a r/w r3_pull_cfg r2_pu ll_cfg r1_pull_cfg r0_pull_cfg 0x18 r_pull_config_b r/w reserved r5_pull_cfg r4_pull_cfg 0x19 r_pull_config_c r/w c3_pull_cfg c2_pull_cfg c1_pull_cfg c0_pull_cfg 0x1a r_pull_config_d r/w reserved c4_pull_cfg 0x1b gpi_int_level_a r/w reserved gpi_6_ int _level gpi_5_ int_level gpi_4_ int_level gpi_3_ int_level gpi_2_ int_level gpi_1_ int_level 0x1c gpi_int_level_b r/w reserved gpi_11_ int_level gpi_10_ int_level gpi_9_ int_level gpi_8_ int_level gpi_7_ int_level 0x1d gpi_event_en_a r/w reserved gpi_6_ event_en gpi_5_ event_en gpi_4_ event_en gpi_3_ event_en gpi_2_ event_en gpi_1_ event_en 0x1e gpi_event_en_b r/w reserved gpi_11_ event_en gpi_10_ event_en gpi_9_ event_en gpi_8_ event_en gpi_7_ event_en 0x1f gpi_interrupt_ en_a r/w reserved gpi_6_ int_en gpi_5_ int_en gpi_4_ int_en gpi_3_ int_en gpi_2_ int_en gpi_1_ int_en 0x20 gpi_interrupt_ en_b r/w reserved gpi_11_ int_en gpi_10_ int_en gpi_9_ int_en gpi_8_ int_en gpi_7_ int_en 0x21 debounce_dis_a r/w reserved gpi_6_ deb_dis gpi_5_ deb_dis gpi_4_ deb _dis gpi_3_ deb_dis gpi_2_ deb_dis gpi_1_ deb_dis 0x22 debounce_dis_b r/w reserved gpi_11_ deb_dis gpi_10_ deb_dis gpi_9_ deb_dis gpi_8_ deb_dis gpi_7_ deb_dis 0x23 gpo_data_ out_a r/w reserved gpo_6_ data gpo_5_ data gpo_4_ data gpo_3_ data gpo_2_ data gpo_1_ data 0x24 gpo_data_ out_b r/w reserved gpo_11_ data gpo_10_ data gpo_9_ data gpo_8_ data gpo_7_ data 0x25 gpo_out_ mode_a r/w reserved gpo_6_ out_mode gpo_5_ out_mode gpo_4_ out_mode gpo_3_ out_mode gpo_2_ out_mode gpo_1_ out_mode 0x26 gpo_out_ m ode_b r/w reserved gpo_11_ out_mode gpo_10_ out_mode gpo_9_ out_mode gpo_8_ out_mode gpo_7_ out_mode 0x27 gpio_ out_en_a r/w reserved gp i o_6_ out _en gp i o_5_ out _en gp i o_4_ out _en gp i o_3_ out _en gp i o_2_ out _en gp i o_1_ out _en 0x28 gpio_out_en_b r/w reserved gp i o_11_ out _en gp i o_10_ out _en gp i o_9_ out _en gp i o_8_ out _en gp i o_7_ out _en
adp5586 data sheet rev. 0 | page 20 of 44 reg add r reg ister name r/w 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2 9 gpio_ inp_en _a r/w reserved gp i o_6_ inp _en gp i o_5_ inp _en gp i o_4_ inp _en gp i o_3_ inp _en gp i o_2_ inp _en gp i o_1_ inp _en 0x2 a gpio_ inp_en _b r/w reserved gp i o_11_ inp _en gp i o_1 0_ inp _en gp i o_9_ inp _en gp i o_8_ inp _en gp i o_7_ inp _en 0x2 b reset_event_a r/w reset_event_ a_level reset_event_a , bits [6:0] 0x2 c reset_event_b r/w reset_event_ b_level reset_event_b , bits[6:0] 0x2 d reset _event_c r/w reset _event_ c_level reset _event_c , b its[6:0] 0x2e reset_cfg r/w reset_pol rst _pass thru_en reset_trig_time , bits [3 :0] reset_pulse_width, bits [1:0] 0x2f pulse_gen_1_ delay r/w pulse_gen_1_delay , bits [7:0] 0x30 pulse_gen_1_ period r/w pulse_gen_1_period , bits [7:0] 0x3 1 pul se_gen_1_ on_time r/w pulse_gen_1_on_time , bits [7:0] 0x32 pulse_gen_2_ delay r/w pulse_gen_2_delay , bits [7:0] 0x3 3 pulse_gen_2_ period r/w pulse_gen_2_period , bits [7:0] 0x3 4 pulse_gen_2_ on_time r/w pulse_gen_2_on_time , bits [7:0] 0x3 5 pulse_gen_ config r/w pulse_ gen_ 1 _inv pulse_ge n_1_ on_clk pulse_ gen_ 1_ prd_clk pulse_ gen_ 1_en pulse_ gen_ 2 _inv pulse_ ge n_2_ on_clk pulse_ gen_ 2_ prd_clk pulse_ gen_ 2_en 0x3 6 logic_cfg r/w reserved ly_inv lc_inv lb_inv la_inv logic_sel , bits [2:0] 0x3 7 logic_ff_cfg r/w reserved ff_set ff_clr 0x3 8 logic_int_ event_en r/w reserved ly_dbnc_ dis logic_ event_en logic_ int_ level 0x39 poll_time_cfg r/w reserved precharge_ time reserved key_poll_time , bits [1:0] 0x3 a pin_config_a r/w reserved r5_config r4_config r3_config r2 _config r1_config r0_config 0x3 b pin_config_b r/w reserved c4_config c3_config c2_config c1_config c0_config 0x3 c pin_config_c r/w pull_select c0_extend_cfg r4_extend _ cfg c1_extend_ cfg r3_extend _ cfg reserved r0_ extend_ cfg 0x3d general_cfg r/w osc_e n osc _freq , bits [1:0] reserved sw_reset int _cfg rst _cfg 0x3 e int_en r/w reserved logic_ien reserved ovrflow_ ien gpi_ien event_ien 1 r m eans read, w means write, and r/w means read/write.
data sheet adp5586 rev. 0 | page 21 of 44 detailed register de scriptions note that a ll register s default to 0000 0000 , unless otherwise specified. id , register 0x00 default: 0011 xxxx (where x = dont care) table 8 . id bit descriptions bits bit name access description [7:4] man_id read only manufacturer id, default = 0011 [3:0] rev_id read only rev ision id int_status , register 0x01 table 9 . int_status bit descriptions bits bit name access description 1 [7 :5] reserved reserved reserved. 4 logic_int read/write 0 = no interrupt. 1 = interrupt due to a general logic condition. 3 reserved reserved reserved. 2 overflow_int read/write 0 = no interrupt. 1 = interrupt due to an overflow condition. 1 gpi_int read/write this bit is not set by a gpi that has been configured to update the fifo and event count. this bit cannot be cleared until all gpi_x_int bits are cleared. 0 = no interrupt. 1 = interrupt due to a general gpi condition. 0 event_int read/write 0 = no interrupt. 1 = interrupt due to key event (press/release), gpi event (gpi programmed for fifo updates) , or logic event (programmed for fifo updates). 1 interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect. status , register 0x02 table 10 . status bit descriptions bits bit name access description 7 reserved reserved reserved. 6 logic_stat read only 0 = output from logic block (ly) is lo w. 1 = output from logic block (ly) is high. 5 reserved reserved reserved. [4:0] ec[4:0] read only event count value. indicates how many events are currently stored on the fifo. fifo_1 , register 0x03 table 11 . fifo_1 bit desc riptions bits bit name access description 7 event1_state read only this bit represents the state of the event that is recorded in the event1_identifier[6:0] bit s. for key events from event 1 to event 36, use the following settings: 1 = key is pres sed. 0 = key is released. for gpi and logic events from event 37 to event 48, use the following settings: 1 = gpi/logic is active. 0 = gpi/logic is inactive. active and inactive states for event 37 to event 48 are programmable. [6:0] event1_identifier[6:0] read only contains the event identifier for the pin. see table 12 for event decoding information .
adp5586 data sheet rev. 0 | page 22 of 44 table 12 . event decoding event no. meaning event no. meaning 0 no event 25 key 25 (r4, c4) 1 key 1 (r0, c0) 26 key 26 (r5, c0) 2 key 2 (r0, c1) 27 key 27 (r5, c1) 3 key 3 (r0, c2) 28 key 28 (r5, c2) 4 key 4 (r0, c3) 29 key 29 (r5, c3) 5 key 5 (r0, c4) 30 key 30 (r5, c4) 6 key 6 (r1, c0) 31 key 31 (r0, gnd) 7 key 7 (r1, c1) 32 ke y 32 (r1, gnd) 8 key 8 (r1, c2) 33 key 33 (r2, gnd) 9 key 9 (r1, c3) 34 key 34 (r3, gnd) 10 key 10 (r1, c4) 35 key 35 (r4, gnd) 11 key 11 (r2, c0) 36 key 36 (r5, gnd) 12 key 12 (r2, c1) 37 gpi 1 (r0) 13 key 13 (r2, c2) 38 gpi 2 (r1) 14 key 14 (r2, c 3) 39 gpi 3 (r2) 15 key 15 (r2, c4) 40 gpi 4 (r3) 16 key 16 (r3, c0) 41 gpi 5 (r4) 17 key 17 (r3, c1) 42 gpi 6 (r5) 18 key 18 (r3, c2) 43 gpi 7 (c0) 19 key 19 (r3, c3) 44 gpi 8 (c1) 20 key 20 (r3, c4) 45 gpi 9 (c2) 21 key 21 (r4, c0) 46 gpi 10 (c3) 22 key 22 (r4, c1) 47 gpi 11 (c4) 23 key 23 (r4, c2) 48 logic 24 key 24 (r4, c3) 49 to 127 unused fifo_2 , register 0x04 table 13 . fifo_2 bit descriptions bits bit name access description 7 event2_state read only see table 11 for bit descriptions . [6:0] event2_identifier[6:0] read only see table 11 for bit descriptions . fifo_3 , register 0x05 table 14 . fifo_3 bit descriptions bits bit name access descrip tion 7 event3_state read only see table 11 for bit descriptions . [6:0] event3_identifier[6:0] read only see table 11 for bit descriptions . fifo_4 , register 0x06 table 15 . fifo_4 bit descriptions bits bit name access description 7 event4_state read only see table 11 for bit descriptions . [6:0] event4_identifier[6:0] read only see table 11 for bit descriptions . fifo_5 , register 0x07 table 16 . fifo_5 bit descriptions bits bit name access description 7 event5_state read only see table 11 for bit descriptions . [6:0] event5_identifier[6:0] read only see tab le 11 for bit descriptions .
data sheet adp5586 rev. 0 | page 23 of 44 fifo_6 register 0x08 table 17 . fifo_6 bit descriptions bits bit name access description 7 event6_state read only see table 11 for bit descriptions . [6:0] event6_identifier[6: 0] read only see table 11 for bit descriptions . fifo_7 , register 0x09 table 18 . fifo_7 bit descriptions bits bit name access description 7 event7_state read only see table 11 for bit descriptions . [6:0] event7_identifier[6:0] read only see table 11 for bit descriptions . fifo_8 , register 0x0a table 19 . fifo_8 bit descriptions bits bit name access description 7 event8_state read o nly see table 11 for bit descriptions . [6:0] event8_identifier[6:0] read only see table 11 for bit descriptions . fifo_9 , register 0x0b table 20 . fifo_9 bit descriptions bits bit name access description 7 event9_state read only see table 11 for bit descriptions . [6:0] event9_identifier[6:0] read only see table 11 for bit descriptions . fifo_10 , register 0x0c table 21 . fifo_10 bit descriptions bits bit name access description 7 event10_state read only see table 11 for bit descriptions . [6:0] event10_identifier[6:0] read only see table 11 for bit descript ions . fifo_11 , register 0x0d table 22 . fifo_11 bit descriptions bits bit name access description 7 event11_state read only see table 11 for bit descriptions . [6:0] event11_identifier[6:0] read only see table 11 for bit descriptions . fifo_12 , register 0x0e table 23 . fifo_12 bit descriptions bits bit name access description 7 event12_state read only see table 11 for bit descriptio ns . [6:0] event12_identifier[6:0] read only see table 11 for bit descriptions . fifo_13 , register 0x0f table 24 . fifo_13 bit descriptions bits bit name access description 7 event13_state read only see table 11 for bit descriptions . [6:0] event13_identifier[6:0] read only see table 11 for bit descriptions .
adp5586 data sheet rev. 0 | page 24 of 44 fifo_14 , register 0x10 table 25 . fifo_14 bit descriptions bits bit name acc ess description 7 event14_state read only see table 11 for bit descriptions . [6:0] event14_identifier[6:0] read only see table 11 for bit descriptions . fifo_15 , register 0x11 table 26 . fifo_15 bit descriptions bits bit name access description 7 event15_state read only see table 11 for bit descriptions . [6:0] event15_identifier[6:0] read only see table 11 for bit descriptions . fifo_16 , register 0x12 table 27 . fifo_16 bit descriptions bits bit name access description 7 event16_state read only see table 11 for bit descriptions . [6:0] event16_identifier[6:0] read only see table 11 for bit descriptions . gpi_int_stat_a , register 0x13 table 28 . gpi_int_stat_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpi_6_int read only 0 = no interrupt 1 = interrupt due to gpi 6 (r5 pin). cleared on read. 4 gpi_5_int read only 0 = no interrupt 1 = interrupt due to gpi 5 (r4 pin). cleared on read. 3 gpi_4_int read only 0 = no interrupt 1 = interrupt due to g pi 4 (r3 pin). cleared on read. 2 gpi_3_int read only 0 = no interrupt 1 = interrupt due to gpi 3 (r2 pin). cleared on read. 1 gpi_2_int read only 0 = no interrupt 1 = interrupt due to gpi 2 (r1 pin). cleared on read. 0 gpi_1_int read only 0 = no interrupt 1 = interrupt due to gpi 1 (r0 pin). cleared on read. gpi_int_stat_b , register 0x14 table 29 . gpi_int_stat_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpi_11_int read only 0 = no interrupt. 1 = inter rupt due to gpi 11 (c4 pin). cleared on read. 3 gpi_10_int read only 0 = no interrupt. 1 = interrupt due to gpi 10 (c3 pin). cleared on read. 2 gpi_9_int read only 0 = no interrupt. 1 = interrupt due to gpi 9 (c2 pin). cleared on read. 1 gpi_8_i nt read only 0 = no interrupt. 1 = interrupt due to gpi 8 (c1 pin). cleared on read. 0 gpi_7_int read only 0 = no interrupt. 1 = interrupt due to gpi 7 (c0 pin). cleared on read.
data sheet adp5586 rev. 0 | page 25 of 44 gpi_status_a , register 0x15 table 30 . gpi_s tatus_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpi_6_stat read only 0 = gpi 6 (r5 pin) is low. 1 = gpi 6 (r5 pin) is high. 4 gpi_5_stat read only 0 = gpi 5 (r4 pin) is low. 1 = gpi 5 (r4 pin) is hig h. 3 gpi_4_stat read only 0 = gpi 4 (r3 pin) is low. 1 = gpi 4 (r3 pin) is high. 2 gpi_3_stat read only 0 = gpi 3 (r2 pin) is low. 1 = gpi 3 (r2 pin) is high. 1 gpi_2_stat read only 0 = gpi 2 (r1 pin) is low. 1 = gpi 2 (r1 pin) is high. 0 g pi_1_stat read only 0 = gpi 1 (r0 pin) is low. 1 = gpi 1 (r0 pin) is high. gpi_status_b , register 0x16 table 31 . gpi_status_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpi_11_stat r ead only 0 = gpi 11 (c4 pin) is low. 1 = gpi 11 (c4 pin) is high. 3 gpi_10_stat read only 0 = gpi 10 (c3 pin) is low. 1 = gpi 10 (c3 pin) is high. 2 gpi_9_stat read only 0 = gpi 9 (c2 pin) is low. 1 = gpi 9 (c2 pin) is high. 1 gpi_8_stat rea d only 0 = gpi 8 (c1 pin) is low. 1 = gpi 8 (c1 pin) is high. 0 gpi_7_stat read only 0 = gpi 7 (c0 pin) is low. 1 = gpi 7 (c0 pin) is high.
adp5586 data sheet rev. 0 | page 26 of 44 r_ pull_config_a , register 0x17 d efault = 0101 0101 table 32. r _ pull_config_a bit d escriptions bits bit name access description [7:6] r3_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [5:4] r2_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [3:2] r1_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [1:0] r0_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor . 11 = disable s all pull - up/pull- down resistors. r_ pull_config_b , register 0x18 default = 0000 0101 table 33. r _ pull_config_b bit descriptions bits bit name access description [7:4] reserved reserved reserved. [3:2] r5_pull_cfg r ead/write reserved except for the adp5586 acbz -01- r7 options . 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [1:0] r4_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resisto r. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. r_ pull_config_c , register 0x19 default = 0 101 0001 table 34. r_ pull_config _c bit descriptions bits bit name access description [7:6] c3_pull_c fg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [5:4] c2_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. [3:2] c1_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resist or. 11 = disable s all pull - up/pull- down resistors. [1:0] c0_pull_cfg read/write 00 = enable s 300 k? pull - up resistor. 01 = enable s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors.
data sheet adp5586 rev. 0 | page 27 of 44 r_ pull_conf ig_d , register 0x1a default = 0000 0001 table 35. r_ pull_config _d bit descriptions bits bit name access description [7:2] reserved reserved reserved . [1:0] c4_pull_cfg read/write 00 = enable s 300 k? pull -up resistor. 01 = enab le s 300 k? pull - down resistor. 10 = enable s 100 k? pull - up resistor. 11 = disable s all pull - up/pull- down resistors. gpi_int_level_a , register 0x1b table 36 . gpi_int_level_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpi_6_int_level read/write 0 = gpi 6 interrupt is active low (gpi_6_int set s whenever r5 is low). 1 = gpi 6 interrupt is active high (gpi_6_int sets whenever r5 is high). 4 gpi_5_int_level read/write 0 = gpi 5 int errupt is active low (gpi_5_int sets whenever r4 is low). 1 = gpi 5 interrupt is active high (gpi_5_int sets whenever r4 is high). 3 gpi_4_int_level read/write 0 = gpi 4 interrupt is active low (gpi_4_int sets whenever r3 is low). 1 = gpi 4 interrupt is active high (gpi_4_int sets whenever r3 is high). 2 gpi_3_int_level read/write 0 = gpi 3 interrupt is active low (gpi_3_int sets whenever r2 is low). 1 = gpi 3 interrupt is active high (gpi_3_int sets whenever r2 is high). 1 gpi_2_int_level re ad/write 0 = gpi 2 interrupt is active low (gpi_2_int sets whenever r1 is low). 1 = gpi 2 interrupt is active high (gpi_2_int sets whenever r1 is high). 0 gpi_1_int_level read/write 0 = gpi 1 interrupt is active low (gpi_1_int sets whenever r0 is low) . 1 = gpi 1 interrupt is active high (gpi_1_int sets whenever r0 is high). gpi_int_level_b , register 0x1c table 37 . gpi_int_level_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpi_11_ int_level read/write 0 = gpi 11 interrupt is active low (gpi_11_int sets whenever r10 is low). 1 = gpi 11 interrupt is active high (gpi_11_int sets whenever r10 is high). 3 gpi_10_int_level read/write 0 = gpi 10 interrupt is active low (gpi_10_int set s whenever r9 is low). 1 = gpi 10 interrupt is active high (gpi_10_int sets whenever r9 is high). 2 gpi_9_int_level read/write 0 = gpi 9 interrupt is active low (gpi_9_int sets whenever r8 is low). 1 = gpi 9 interrupt is active high (gpi_9_int set s whenever r8 is high). 1 gpi_8_int_level read/write 0 = gpi 8 interrupt is active low (gpi_8_int sets whenever r7 is low). 1 = gpi 8 interrupt is active high (gpi_8_int sets whenever r7 is high). 0 gpi_7_int_level read/write 0 = gpi 7 interrupt is a ctive low (gpi_7_int sets whenever r6 is low). 1 = gpi 7 interrupt is active high (gpi_7_int sets whenever r6 is high).
adp5586 data sheet rev. 0 | page 28 of 44 gpi_event_en_a , register 0x1d table 38 . gpi_event_en_a bit descriptions bits bit name access description [ 7:6] reserved reserved reserved. 5 gpi_6_event_en read/write 0 = disable s gpi events from gpi 6. 1 = allow s gpi 6 activity to generate events on the fifo . 1 4 gpi_5_event_en read/write 0 = disable s gpi events from gpi 5. 1 = allow s gpi 5 activity to generate events on the fifo . 1 3 gpi_4_event_en read/write 0 = disable s gpi events from gpi 4. 1 = allow s gpi 4 activity to generate events on the fifo . 1 2 gpi_3_event_en read/write 0 = disable s gpi events from gpi 3. 1 = allow s gpi 3 activity to generate events on the fifo . 1 1 gpi_2_event_en read/write 0 = disable s gpi events from gpi 2. 1 = allow s gpi 2 activity to generate events on the fifo . 1 0 gpi_1_event_en read/write 0 = disable s gpi events from gpi 1. 1 = allow s gpi 1 activity to generate events on the fifo . 1 1 gpis in this mode are considered fifo events and can be used for unlock purposes. gpi activity in this mode causes event _int interrupts. gpis in this mod e do not generate gpi_int interrupts. gpi_event_en_b , register 0x1e table 39 . gpi_event_en_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpi_11_event_en read/write 0 = disable s gpi events from gpi 11. 1 = allow s g pi 11 activity to generate events on the fifo . 1 3 gpi_10_event_en read/write 0 = disable s gpi events from gpi 10. 1 = allow s gpi 10 activity to generate events on the fifo . 1 2 gpi_9_event_en read/write 0 = disable s gpi events from gpi 9. 1 = allo ws gpi 9 activity to generate events on the fifo . 1 1 gpi_8_event_en read/write 0 = disable s gpi events from gpi 8. 1 = allow s gpi 8activity to generate events on the fifo . 1 0 gpi_7_event_en read/write 0 = disable s gpi events from gpi 7. 1 = allow s gpi 7 activity to generate events on the fifo . 1 1 gpis in this mode are considered fifo events and can be used for unlock purposes. gpi activity in this mode cause s event_int interrupts. gpis in this mode do not generate gpi_int interrupts.
data sheet adp5586 rev. 0 | page 29 of 44 gpi_interr upt_en_a , register 0x1f table 40 . gpi_interrupt_en_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpi_6_int_en read/write 0 = gpi_6_int is disabled. 1 = gpi_6_int enabled. asserts the g pi_int bit (register 0x01, bit 1) if gpi_6_int is set and the gpi 6 interrupt condition is met. 4 gpi_5_int_en read/write 0 = gpi_5_int is disabled. 1 = gpi_5_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_5_int is set and the gpi 5 interrupt condition is met. 3 gpi_4_int_en read/write 0 = gpi_4_int is disabled. 1 = gpi_4_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_4_int is set and the gpi 4 interrupt condition is met. 2 gpi_3_int_en read/write 0 = gpi_3 _int is disabled. 1 = gpi_3_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_3_int is set and the gpi 3 interrupt condition is met. 1 gpi_2_int_en read/write 0 = gpi_2_int is disabled. 1 = gpi_2_int enabled. asserts the gpi_in t b it (register 0x01, bit 1) if gpi_2_int is set and the gpi 2 interrupt condition is met. 0 gpi_1_int_en read/write 0 = gpi_1_int is disabled. 1 = gpi_1_int enabled. asserts the gpi_in t bit (register 0x01, bit 1) if gpi_1_int is set and the gpi 1 interr upt condition is met. gpi_interrupt_en_b , register 0x20 table 41 . gpi_interrupt_en_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpi_11_int_en read/write 0 = gpi_11_int is disabled. 1 = gpi_11_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_11_int is set and the gpi 11 interrupt condition is met. 3 gpi_10_int_en read/write 0 = gpi_10_int is disabled. 1 = gpi_10_int enabled. asserts the gpi_in t bit (register 0x01 , bit 1) if gpi_10_int is set and the gpi 10 interrupt condition is met. 2 gpi_9_int_en read/write 0 = gpi_9_int is disabled. 1 = gpi_9_int enabled. asserts the gpi_in t bit (register 0x01, bit 1) if gpi_9_int is set and the gpi 9 interrupt condition i s met. 1 gpi_8_int_en read/write 0 = gpi_8_int is disabled. 1 = gpi_8_int enabled. asserts the gpi_in t bit (register 0x01, bit 1) if gpi_8_int is set and the gpi 8 interrupt condition is met. 0 gpi_7_int_en read/write 0 = gpi_7_int is disabled. 1 = gpi_7_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_7_int is set and the gpi 7 interrupt condition is met.
adp5586 data sheet rev. 0 | page 30 of 44 debounce_dis_a , register 0x21 table 42 . debounce_dis_a bit descriptions bits bit name access descrip tion [7:6] reserved reserved reserved. 5 gpi_6_deb_dis read/write 0 = debounce enabled on gpi 6. 1 = debounce disabled on gpi 6. 4 gpi_5_deb_dis read/write 0 = debounce enabled on gpi 5. 1 = debounce disabled on gpi 5. 3 gpi_4_deb_dis read/writ e 0 = debounce enabled on gpi 4. 1 = debounce disabled on gpi 4. 2 gpi_3_deb_dis read/write 0 = debounce enabled on gpi 3. 1 = debounce disabled on gpi 3. 1 gpi_2_deb_dis read/write 0 = debounce enabled on gpi 2. 1 = debounce disabled on gpi 2. 0 gpi_1_deb_dis read/write 0 = debounce enabled on gpi 1. 1 = debounce disabled on gpi 1. debounce_dis_b , register 0x22 table 43 . debounce_dis_b bit descriptions bits bit name access description [7:5] reserved reserved res erved. 4 gpi_11_deb_dis read/write 0 = debounce enabled on gpi 11. 1 = debounce disabled on gpi 11. 3 gpi_10_deb_dis read/write 0 = debounce enabled on gpi 10. 1 = debounce disabled on gpi 10. 2 gpi_9_deb_dis read/write 0 = debounce enabled on g pi 9. 1 = debounce disabled on gpi 9. 1 gpi_8_deb_dis read/write 0 = debounce enabled on gpi 8. 1 = debounce disabled on gpi 8. 0 gpi_7_deb_dis read/write 0 = debounce enabled on gpi 7. 1 = debounce disabled on gpi 7. gpo_data_out_a , registe r 0x23 table 44 . gpo_data_out_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpo_6_ data read/write 0 = sets output low. 1 = sets output high. 4 gpo_5_ data read/write 0 = sets output lo w. 1 = sets output high. 3 gpo_4_data read/write 0 = sets output low. 1 = sets output high. 2 gpo_3_ data read/write 0 = sets output low. 1 = sets output high. 1 gpo_2_ data read/write 0 = sets output low. 1 = sets output high. 0 gpo_1_da ta read/write 0 = sets output low. 1 = sets output high.
data sheet adp5586 rev. 0 | page 31 of 44 gpo_data_out_b , register 0x24 table 45 . gpo_data_out_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpo_11_ data read/write 0 = sets output low. 1 = sets output high. 3 gpo_10_ data read/write 0 = sets output l ow. 1 = sets output high. 2 gpo_9_ data read/write 0 = sets output low. 1 = sets output high. 1 gpo_8_ data read/write 0 = sets output low. 1 = sets output hi gh. 0 gpo_7_data read/write 0 = sets output low. 1 = sets output high. gpo_out_mode_a , register 0x25 table 46 . gpo_out_mode_a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 gpo_6_out_mo de read/write 0 = push - pull. 1 = open drain. 4 gpo_5_out_mode read/write 0 = push - pull. 1 = open drain. 3 gpo_4_out_mode read/write 0 = push - pull. 1 = open drain. 2 gpo_3_ out_mode read/write 0 = push - pull. 1 = open drain. 1 gpo_2_out_m ode read/write 0 = push - pull. 1 = open drain. 0 gpo_1_out_mode read/write 0 = push - pull. 1 = open drain. gpo_out_mode_b , register 0x26 table 47 . gpo_out_mode_b bit descriptions bits bit name access description [7:5] reser ved reserved reserved. 4 gpo_11_out_mode read/write 0 = push - pull. 1 = open drain. 3 gpo_10_out_mode read/write 0 = push - pull. 1 = open drain. 2 gpo_9_out_mode read/write 0 = push - pull. 1 = open drain. 1 gpo_8_out_mode read/write 0 = push -p ull. 1 = open drain. 0 gpo_7_out_mode read/write 0 = push - pull. 1 = open drain.
adp5586 data sheet rev. 0 | page 32 of 44 gpio_ out_en_a , register 0x27 table 48 . gpio_ out _ en_ a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 g pio_6_ out _en read/write 0 = gpio 6 output disabled . 1 = gpio 6 output enabled . 4 gpio_5_ out _en read/write 0 = gpio 5 output disabled . 1 = gpio 5 output enabled . 3 gpio_4_ out _en read/write 0 = gpio 4 output disabled . 1 = gpio 4 output enabled . 2 gpio_3_ out _en read/write 0 = gpio 3 output disabled . 1 = gpio 3 output enabled . 1 gpio_2_ out _en read/write 0 = gpio 2 output disabled . 1 = gpio 2 output enabled . 0 gpio_1_ out _en read/write 0 = gpio 1 output disabled . 1 = gpio 1 output ena bled . gpio_ out_en_b , register 0x28 table 49 . gpio_ out _ en_ b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpio_11_ out _en read/write 0 = gpio 11 output disabled . 1 = gpio 11 output enable d. 3 gpio_10_ out _en read/write 0 = gpio 10 output disabled . 1 = gpio 10 output enabled . 2 gpio_9_ out _en read/write 0 = gpio 9 output disabled . 1 = gpio 9 output enabled . 1 gpio_8_ out _en read/write 0 = gpio 8 output disabled . 1 = gpio 8 outpu t enabled . 0 gpio_7_ out _en read/write 0 = gpio 7 output disabled . 1 = gpio 7 output enabled . gpio_inp_en _a , register 0x2 9 table 50 . gpio_ inp_en _a bit descriptions bits bit name access description [7:6] reserved reserved reser ved. 5 gpio_6_ inp _en read/write 0 = gpio 6 input disabled . 1 = gpio 6 input enabled . 4 gpio_5_ inp _en read/write 0 = gpio 5 input disabled . 1 = gpio 5 input enabled . 3 gpio_4_ inp _en read/write 0 = gpio 4 input disabled . 1 = gpio 4 input enabl ed . 2 gpio_3_ inp _en read/write 0 = gpio 3 input disabled . 1 = gpio 3 input enabled . 1 gpio_2_ inp _en read/write 0 = gpio 2 input disabled . 1 = gpio 2 input enabled . 0 gpio_1_ inp _en read/write 0 = gpio 1 input disabled . 1 = gpio 1 input enable d.
data sheet adp5586 rev. 0 | page 33 of 44 gpio_inp_en_b, register 0x2a table 51. gpio_inp_en_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 gpio_11_inp_en read/write 0 = gpio 11 input disabled. 1 = gpio 11 input enabled. 3 gpio_10_inp_en read/write 0 = gpio 10 input disabled. 1 = gpio 10 input enabled. 2 gpio_9_inp_en read/write 0 = gpio 9 input disabled. 1 = gpio 9 input enabled. 1 gpio_8_inp_en read/write 0 = gpio 8 input disabled. 1 = gpio 8 input enabled. 0 gpio_7_inp_en read/write 0 = gpio 7 input disabled. 1 = gpio 7 input enabled. reset_event_a, register 0x2b table 52. reset_event_a bit descriptions bits bit name access description 7 reset_event_a_level read/write defines which level the first reset event should be to generate the reset_out signal. for key events, use the following settings: 0 = inactive event used as a reset condition. 1 = active event used as a reset condition. for gpis and logic outputs configured for fifo updates, use the following settings: 0 = not applicable; releases no t used for reset generation. 1 = press is used as a reset event. [6:0] reset_event_a[6:0] read/write defines an event that can be used to generate the reset_out signal. up to three events can be defined for generating the reset_out signal, using reset_event_a[6:0], reset_event_b[6:0], and reset_event_c[6:0]. if one of the registers is 0, that register is not used for reset generation. all reset events must be detected at the same time to trigger the reset. reset_event_b, register 0x2c table 53. reset_event_b bit descriptions bits bit name access description 7 reset_event_b_level read/write defines which level the second reset even t should be to generate the reset_out signal. refer to table 52. [6:0] reset_event_b[6:0] read/write defines an event that ca n be used to generate the reset_out signal. see table 12. reset_event_c, register 0x2d table 54. reset_event_c bit descriptions bits bit name access description 7 reset_event_c_level read/write defines which level the third reset event should be to generate the reset_out signal. refer to table 52. [6:0] reset_event_c[6:0] read/write defines an event that ca n be used to generate the reset_out signal. see table 12.
adp5586 data sheet rev. 0 | page 34 of 44 reset_cfg, register 0x2e table 55. reset_cfg bit descriptions bits bit name access description 7 reset_pol read/write sets the polarity of the reset_out signal. 0 = reset_out is active low. 1 = reset_out is active high. 6 rst _passthru_en read/write allows the rst pin to override (or with) the reset_out signal. [5:2] reset_trig_time[3:0] read/write defines the length of time that the reset events must be active before a reset_out signal is generated. all events must be acti ve at the same time for the same duration. 0000 = immediate. 0001 = 1.0 sec. 0010 = 1.5 sec. 0011 = 2.0 sec. 0100 = 2.5 sec. 0101 = 3.0 sec. 0110 = 3.5 sec. 0111 = 4.0 sec. 1000 = 5.0 sec. 1001 = 6.0 sec. 1010 = 7.0 sec. 1011 = 8.0 sec. 1100 = 9.0 sec. 1101 = 10.0 sec. 1110 = 11.0 sec. 1111 = 12.0 sec. [1:0] reset_pulse_width[1:0] read/write defines the pulse width of the reset_out signal. 00 = 500 s. 01 = 1 ms. 10 = 2 ms. 11 = 10 ms. pulse_gen_1_delay, register 0x2f table 56. pulse_gen_1_delay bit descriptions bits bit name access description [7:0] pulse_gen_1_delay[7:0] read/write defines initial delay fr om the first clock of the first enable of pulse generator 1. delay is defined as the number of clock cycles of the chosen period clock speed (see register 0x35). for example, pulse_gen_1_delay pulse_gen_1_prd_clk 0 1 0000 0000 0 0 ms 0000 0001 1 125 ms 0000 0010 2 250 ms 0000 0011 3 375 ms 0000 0100 4 500 ms 1111 1110 254 ms 31.750 sec 1111 1111 255 ms 31.875 sec
data sheet adp5586 rev. 0 | page 35 of 44 pulse_gen_1_period , registe r 0x30 table 57. pulse_ gen_1_period bit descriptions bits bit name access description [7:0] pulse_gen_1_period [7:0] read/write defines period of pulse generator 1. period is defined as the number of clock cycles of the chosen period clock speed (see register 0x35). for example, pulse_gen_1_ period pulse_gen_1_prd_clk 0 1 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 1111 1110 1111 111 1 0 ms 1 ms 2 ms 3 ms 4 ms 254 ms 255 ms 0 ms 125 ms 250 ms 375 ms 500 ms 31.7 50 sec 31.875 sec pulse_gen_1_on_time , register 0x3 1 table 58 . pulse_gen_1_on_time bit descriptions bits bit name access description [7:0] pulse_gen_1_on_time [7:0] read/write defines on time of pulse generator 1. on time is defin ed as the number of clock cycles of the chosen clock speed (see register 0x35). for example, pulse_gen_1_ on_time pulse_gen_1_on_clk 0 1 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 1111 1110 1111 111 1 0 ms 1 ms 2 ms 3 ms 4 ms 254 ms 2 55 ms 0 ms 125 ms 250 ms 375 ms 500 ms 31.750 sec 31.875 sec pulse_gen_2_delay , register 0x32 table 59 . pulse_gen_2_delay bit descriptions bits bit name access description [7:0] pulse_gen_2_delay [7:0] read/write defines initial delay fr om the first clock of the first enable of pulse generator 2 . delay is defined as the number of clock cycles of the chosen p eriod clock speed (see register 0x35). for example, pulse_gen_ 2_ delay pulse_gen_2_prd_clk 0 1 0000 0000 0000 00 01 0000 0010 0000 0011 0000 0100 1111 1110 1111 111 1 0 ms 1 ms 2 ms 3 ms 4 ms 254 ms 255 ms 0 ms 125 ms 250 ms 375 ms 500 ms 31.750 sec 31.875 sec
adp5586 data sheet rev. 0 | page 36 of 44 pulse_gen_2_period , register 0x33 table 60 . pulse_gen_2_period bit descriptio ns bits bit name access description [7:0] pulse_gen_2_period [7:0] read/write defines period of pulse g enerator 2 . period is defined as the number of clock cycles of the chosen period clock speed (see register 0x35). for example, pulse_gen_ 2_ period pul se_gen_2_prd_clk 0 1 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 1111 1110 1111 111 1 0 ms 1 ms 2 ms 3 ms 4 ms 254 ms 255 ms 0 ms 125 ms 250 ms 375 ms 500 ms 31.750 sec 31.875 sec pulse_gen_2_on_time , register 0x 34 table 61 . pulse_gen_2_on_time bit descriptions bits bit name access description [7:0] pulse_gen_2_ on_time [7:0] read/write defines on time of pulse g enerator 2 . on time is defined as the number of clock cycles of the chosen clock speed (see register 0x35). for example, pulse_gen_ 2_ on_time pulse_gen_ 2 _on_clk 0 1 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 1111 1110 1111 111 1 0 ms 1 ms 2 ms 3 ms 4 ms 254 ms 255 ms 0 ms 125 ms 250 ms 375 ms 500 ms 31.750 sec 31.875 sec
data sheet adp5586 rev. 0 | page 37 of 44 pulse_gen_config , register 0x3 5 table 62. pulse_gen_config bit descriptions bits bit name access description 7 pulse_gen_1_inv read/write 0 = no inversion on pulse generator 1. o n time is defined as the length of time a high signal is output. 1 = inverted output on pulse g enerator 1. on time is defined as the length of time a high signal is output. 6 pulse_gen_1_on_clk read/write defines clock speed for the on time of pulse generator 1 . 0 = 1 ms. 1 = 125 ms. setting pulse_gen_1_on_clk = 1 and pulse_gen_1_prd_clk = 0 is not a supported configuration. 5 pulse_gen_1_prd_clk read/write defines clock speed for the period of pulse g enerato r 1 . 0 = 1 ms. 1 = 125 ms. setting pulse_gen_1_on_clk = 1 and pulse_gen_1_prd_clk = 0 is not a supported config uration. 4 pulse_gen_1_en read/write 0 = pulse g enerator 1 is disabled. the off signal is output constantly. 1= pulse g enerator 1 is enabled. 3 pulse_gen_2_inv read/write 0 = no inversion on pulse generator 2. on time is defined as the length of time a h igh signal is output . 1 = i nverted output on pulse g enerator 2. on time is defined as the length of time a low signal is output . 2 pulse_gen_ 2 _on_clk read/write defines clock speed for the on time of pulse generator 2. 0 = 1 ms. 1 = 125 ms. setting pulse_ gen_2_on_clk = 1 and pulse_gen_2_prd_clk = 0 is not a supported configuration. 1 pulse_gen_2_prd_clk read/write defines clock speed for the period of pulse generator 2 . 0 = 1 ms. 1 = 125 ms. setting pulse_gen_2_on_clk = 1 and pulse_gen_2_prd_clk = 0 is no t a supported configuration. 0 pulse_gen_2_en read/write 0 = pulse generator 2 is disabled. the off signal is output constantly. 1 = pulse generator 2 is enabled. logic_cfg , register 0x3 6 table 63 . logic_cfg bit descriptions bits bit name access description 7 reserved reserved reserved. 6 ly_inv read/write 0 = the ly output is not inverted before passing into the logic block. 1 = inverts the ly output from the logic block. 5 lc_inv read/write 0 = the lc input is not inverted bef ore passing into the logic block. 1 = inverts lc input before passing it into the logic block. 4 lb_inv read/write 0 = the lb input is not inverted before passing into the logic block. 1 = inverts lb input before passing it into the logic block. 3 la_inv read/write 0 = the la input is not inverted before passing into the logic block. 1 = inverts la input before passing it into the logic block. [2:0] logic_sel[2:0] read/write configures the digital mux for the logic block. refer to figure 19 . 000 = off/disable. 001 = and. 010 = or. 011 = xor. 100 = ff. 101 = in_la. 110 = in_lb. 111 = in_lc.
adp5586 data sheet rev. 0 | page 38 of 44 logic_ff_cfg , register 0x3 7 table 64 . logic_ff_cfg bit descriptions bits bit name access description [7:2] reserved reserved reserved. 1 ff_set read/write 0 = ff not set in the logic block. refer to figure 19 . 1 = set s ff in the logic block. 0 ff_clr read/write 0 = ff not cleared in the logic block. refer to figure 19 . 1 = clear s ff in the logic block. logic_int_event_en , register 0x3 8 table 65 . logic_int_event_en bit descriptions bits bit name access description [7:3] reserved reserved reserved . 2 ly_dbnc_dis read/write 0 = output of the logic block is debounced before entering the event/interrupt block. 1 = output of the logic block is not debounced before entering the event/interrupt block. use with caution because glitches may generate inter rupts prematurely. 1 logic_event_en read/write 0 = ly cannot generate interrupt. 1 = allow s ly activity to generate events on the fifo. 0 logic_int_level read/write configure s the logic level of ly that generates an interrupt. 0 = ly is active low. 1 = ly is active high. poll_time_cfg , register 0x3 9 table 66 . poll_time_cfg bit descriptions bits bit name access description [7:4] reserved reserved reserved. 3 precharge_time read/write defines time to allow pre charge. 0 = 100 s. 1 = 200 s. 2 reserved reserved reserved. [1:0] key_poll_time[1:0] read/write configure s time between consecutive scan cycles. 00 = 10 ms. 01 = 20 ms. 10 = 30 ms. 11 = 40 ms. pin_config_a , register 0x3 a table 67 . pin_config_ a bit descriptions bits bit name access description [7:6] reserved reserved reserved. 5 r5_config read/write 0 = gpio 6. 1 = row 5. 4 r4_config read/write 0 = gpio 5 (see r4_extend_cfg in table 69 for alternate configuration, reset) . 1 = row 4 3 r3_config read/write 0 = gpio 4 (see r3_extend_cfg in table 69 for alternate configuration , lc). 1 = row 3 2 r2_config read/write 0 = gpio 3 1 = row 2 1 r1_config read/write 0 = gpio 2 1 = row 1 0 r0_config read/write 0 = gpio 1/ly (see r0_extend_cfg in table 69 f or alternate configuration, ly). 1 = row 0
data sheet adp5586 rev. 0 | page 39 of 44 pin_config_b, register 0x3b table 68. pin_config_b bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 c4_config read/write 0 = gpio 11. 1 = column 4. 3 c3_config read/write 0 = gpio 10. 1 = column 3. 2 c2_config read/write 0 = gpio 9. 1 = column 2. 1 c1_config read/write 0 = gpio 8 (see c1_extend_cfg in table 69 for alternate configuration, pulse_gen_2 ) . 1 = column 1. 0 c0_config read/write 0 = gpio 7 (see c0_extend_cfg in table 69 for alternate configuration, pulse_gen_1 ). 1 = column 0. pin_config_c, register 0x3c table 69. pin_config_c bit descriptions bits bit name access description 7 pull_select read/write 0 = 300 k resistor used for row pull-up during key scanning. 1 = 100 k resistor used for row pull-up during key scanning. 6 c0_extend_cfg read/write 0 = c0 remains configured as gpio 7. 1 = c0 reconfigured as pulse_gen_1 output. 5 r4_extend_cfg read/write 0 = r4 remains configured as gpio 5. 1 = r4 reconfigured as reset_out output. 4 c1_extend_cfg read/write 0 = c1 remains configured as gpio 8. 1 = c1 reconfigured as pulse_gen_2 output. 3 r3_extend_cfg read/write 0 = r3 remains configured as gpio 4. 1 = r3 reconfigured as lc input for the logic block. [2:1] reserved reserved reserved. 0 r0_extend_cfg read/write 0 = r0 remains configured as gpio 1. 1 = r0 reconfigured as ly output from the logic block. general_cfg, register 0x3d table 70. general_cfg bit descriptions bits bit name access description 7 osc_en read/write 0 = disables internal 800 khz oscillator. 1 = enables internal 800 khz oscillator. [6:5] osc_freq[1:0] read/write sets the input clock frequency fed from the base 800 khz oscillator to the digital core. slower frequencies result in less quiescent current, but key and gpi scan times increase. 00 = 50 khz. 01 = 100 khz. 10 = 200 khz. 11 = 400 khz. [4:3] reserved reserved reserved. 2 sw_reset read/write software reset. set to 1 to reset the adp5586 . this function is similar to bringing rst low, then high. wait at least 200 s before reprogramming the device. 1 int _cfg read/write configures the behavior of the int pin if the user tries to clear it while an interrupt is pending. 0 = int pin remains asserted if an interrupt is pending. 1 = int pin deasserts for 50 s and reasserts if an interrupt is pending. 0 rst _cfg read/write configures the response of the adp5586 to the rst pin and the sw_reset bit. 0 = the adp5586 resets if rst is low. 1 = the adp5586 does not reset if rst is low.
adp5586 data sheet rev. 0 | page 40 of 44 int_en , register 0x3 e table 71 . int_en bit descriptions bits bit name access description [7:5] reserved reserved reserved. 4 logic_ien read/write 0 = logic 1 interrupt is disabled. 1 = assert s the int pin if the logic_int bit is set (register 0x01, bit 4) . 3 reserved reserved reserved. 2 ovrflow_ien read/write 0 = overflow interrupt is disabled. 1 = assert s the int pin if the ovrflow_int bit is set (registe r 0x01, bit 2) . 1 gpi_ien read/write 0 = gpi interrupt is disabled. 1 = assert s the int pin if the gpi_int is set (register 0x01, bit 1) . 0 event_ien read/write 0 = event interrupt is disabled. 1 = assert s the int pin if the event_int is set (register 0x01, bit 0) .
data sheet adp5586 rev. 0 | page 41 of 44 applications schematic sda scl rst int logic reset gen oscill at or registers vdd gnd host processor kp/logic output/gpi/gpo kp/logic input/gpi/gpo kp/logic input/gpi/gpo kp/logic input/gpi/gpo kp/reset output/gpi/gpo sda scl rst int vdd vdd r2 r1 r0 r4 r3 c4 c3 c2 c1 c0 54321 10 987 6 15141312 11 2019181716 2524232221 adp5586 gpi scan and decode pulse gen 1 pulse gen 2 ke y scan and decode uvlo por i 2 c inter f ace i/o config 11148-028 figure 28 . typical application s schematic
adp5586 data sheet rev. 0 | page 42 of 44 outline dimensions 01-20-2011-a a b c d 0.545 0.500 0.455 side view 0.230 0.200 0.170 0.300 0.260 0.220 coplanarity 0.05 seating plane 1 2 3 4 bottom view (ball side up) top view (ball side down) ball 1 identifier 0.40 ref 1.20 ref 1.630 1.590 sq 1.550 figure 29 . 16 - ball wafer level chip scale pack age [wlcsp] (cb - 16 - 10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp5586acbz - 00- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5586acbz - 01- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5586acbz - 03- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5586cb - evalz wlcsp evaluation board cb - 16- 10 1 z = rohs compliant part.
data sheet adp5586 rev. 0 | page 43 of 44 notes
adp5586 data sheet rev. 0 | page 44 of 44 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11148 -0- 3/13(0)

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